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NCP1571 Low Voltage Synchronous Buck Controller
The NCP1571 is a low voltage buck controller. It provides the control for a DC-DC power solution producing an output voltage as low as 0.980 V over a wide current range. The NCP1571-based solution is powered from 12 V with the output derived from a 2-7 V supply. It contains all required circuitry for a synchronous NFET buck regulator using the V2t control method to achieve the fastest possible transient response and best overall regulation. NCP1571 operates at a fixed internal 200 kHz frequency and is packaged in an SOIC-8. This device provides undervoltage lockout protection, Soft-Start, Power Good with delay, and built-in adaptive non-overlap. During undervoltage lockout, the NCP1571 controller allows the power supply output to drift down, allowing the load time to shut off. This operation distinguishes the NCP1571 from other parts in its family.
Features http://onsemi.com MARKING DIAGRAM
8 8 1 SOIC-8 D SUFFIX CASE 751 1 A L Y W = Assembly Location = Wafer Lot = Year = Work Week 1571 ALYW
* * * * * * * * * * * * * * *
Pb-Free Package is Available 0.980 V 1.0% Reference Voltage V2 Control Topology 200 ns Transient Response Programmable Soft-Start Power Good Programmable Power Good Delay 40 ns Gate Rise and Fall Times (3.3 nF Load) Adaptive FET Non-Overlap Time Fixed 200 kHz Oscillator Frequency Undervoltage Lockout Holds Both Gate Outputs Low On/Off Control Through Use of the COMP Pin Overvoltage Protection through Synchronous MOSFETs Synchronous N-Channel Buck Design Dual Supply, 12 V Control, 2-7 V Power Source
PIN CONNECTIONS
VCC PWRGD PGDELAY COMP 1 8 GND VFB GATE(L) GATE(H)
ORDERING INFORMATION
Device NCP1571D NCP1571DR2 NCP1571DR2G Package SOIC-8 SOIC-8 SOIC-8 (Pb-Free) Shipping 98 Units/Rail 2500 Tape & Reel 2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2004
1
October, 2004 - Rev. 4
Publication Order Number NCP1571/D
NCP1571
12 V PWRGD VLOGIC R1 50 k C4 0.47 mF R4 10 PWRGD NCP1571 PGDELAY COMP C13 0.1 mF VFB VCC GND 100 pF C6 NTD4302 Q1 2.7 mH L1
+ + + +
GND
5.0 V 33 mF/8.0 V/1.6 Arms C1
+ +
C2
+
C3
2.5 V/10 A
GATE(L) GATE(H)
NTD4302 Q2
5.1 k R3
C8
C9
C10
C11 GND
C12 0.01 mF
R5 3.3 k
56 mF/4.0 V/1.6 Arms SP-CAP 40 mW
Figure 1. Applications Circuit MAXIMUM RATINGS
Rating Operating Junction Temperature Storage Temperature Range ESD Susceptibility (Human Body Model) Lead Temperature Soldering: Moisture Sensitivity Level Package Thermal Resistance, SOIC-8 Junction-to-Case, RqJC Junction-to-Ambient, RqJA Reflow: (Note 1) Value 150 -65 to 150 2.0 230 peak 2 48 165 Unit C C kV C - C/W C/W
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. 60 second maximum above 183C.
MAXIMUM RATINGS
Pin Name IC Power Input Compensation Capacitor Voltage Feedback Input Power Good Output Power Good Delay High-Side FET Driver Low-Side FET Driver Ground Pin Symbol VCC COMP VFB PWRGD PGDELAY GATE(H) GATE(L) GND VMAX 15 V 6.0 V 6.0 V 15 V 6.0 V 15 V 15 V 0.5 V VMIN -0.5 V -0.5 V -0.5 V -0.5 V -0.5 V -0.5 V -2.0 V for 50 ns -0.5 V -2.0 V for 50 ns -0.5 V ISOURCE N/A 10 mA 1.0 mA 1.0 mA 1.0 mA 1.5 A Peak 200 mA DC 1.5 A Peak 200 mA DC 1.5 A Peak 450 mA DC ISINK 1.5 A Peak 450 mA DC 10 mA 1.0 mA 20 mA 10 mA 1.5 A Peak 200 mA DC 1.5 A Peak 200 mA DC N/A
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ELECTRICAL CHARACTERISTICS (0C < TJ < 125C, 11.4 V < VCC < 12.6 V, CGATE(H) = CGATE(L) = 3.3 nF, CPGDELAY = 0.01 mF, CCOMP = 0.1 mF; unless otherwise specified.)
Characteristic Error Amplifier VFB Bias Current COMP Source Current COMP Sink Current Reference Voltage COMP Max Voltage COMP Min Voltage COMP Fault Discharge Current at UVLO COMP Fault Discharge Threshold to Reset UVLO Open Loop Gain Unity Gain Bandwidth PSRR @ 1.0 kHz Output Transconductance Output Impedance GATE(H) and GATE(L) Rise Time Fall Time GATE(H) to GATE(L) Delay GATE(L) to GATE(H) Delay Minimum Pulse Width High Voltage (AC) 1.0 V < GATE(L), GATE(H) < VCC - 2.0 V VCC - 2.0 V < GATE(L), GATE(H) < 1.0 V GATE(H) < 2.0 V, GATE(L) > 2.0 V GATE(L) < 2.0 V, GATE(H) > 2.0 V GATE(X) = 4.0 V Measure GATE(L) or GATE(H) 0.5 nF < CGATE(H) = CGATE(L) < 10 nF Note 2 Measure GATE(L) or GATE(H) 0.5 nF < CGATE(H) = CGATE(L) < 10 nF Note 2 Resistance to GND. Note 2 - - 40 40 - VCC - 0.5 40 40 60 60 250 VCC 80 80 100 100 - - ns ns ns ns ns V VFB = 0 V COMP = 1.5 V, VFB = 0.8 V COMP = 1.5 V, VFB = 1.2 V COMP = VFB TJ < 25C VFB = 0.8 V VFB = 1.2 V COMP = 1.2 V, VCC = 6.9 V - - - - - - - 15 15 0.970 0.965 2.4 - 0.5 0.1 - - - - - 0.2 30 30 0.980 0.980 2.7 0.1 1.7 0.25 98 20 70 32 2.5 2.0 60 60 0.990 0.995 - 0.2 - 0.3 - - - - - mA mA mA V V V V mA V dB kHz dB mmho MW Test Conditions Min Typ Max Unit
Low Voltage (AC)
-
0
0.5
V
GATE(H)/(L) Pulldown Power Good Lower Threshold, VO Rising
20
50
115
kW
TJ < 25C Lower Threshold, VO Falling TJ < 25C PWRGD Low Voltage Delay Charge Current Delay Clamp Voltage Delay Charge Threshold Delay Discharge Current at UVLO ISINK = 1.0 mA, VFB = 0 V PGDELAY = 2.0 V - Ramp PGDELAY, Monitor PWRGD PGDELAY = 0.5 V, VCC = 6.9 V
0.852 0.847 0.663 0.658 - 7.0 3.45 3.1 0.5
0.882 0.882 0.685 0.685 0.15 12 4.0 3.3 2.0
0.912 0.917 0.709 0.714 0.4 18 4.3 3.5 -
V V V V V mA V V mA
2. Guaranteed by design. Not tested in production.
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ELECTRICAL CHARACTERISTICS (continued) (0C < TJ < 125C, 11.4 V < VCC < 12.6 V, CGATE(H) = CGATE(L) = 3.3 nF, CPGDELAY = 0.01 mF, CCOMP = 0.1 mF; unless otherwise specified.)
Characteristic Power Good Delay Discharge Threshold to Reset UVLO PGDELAY = 0.5 V, VCC = 12 V to 6.9 to 12 V, Ramp PGDELAY to 0.1 V, Monitor I (PGDELAY) With 0.01 mF. Note 3 0.1 0.25 0.3 V Test Conditions Min Typ Max Unit
"Good" Signal Delay PWM Comparator PWM Comparator Offset Ramp Max Duty Cycle Artificial Ramp Transient Response VFB Input Range Oscillator Switching Frequency General Electrical Specifications VCC Supply Current Start Threshold Stop Threshold Hysteresis
1.0
3.0
5.0
ms
VFB = 0 V, Increase COMP Until GATE(H) Starts Switching - Duty Cycle = 50% COMP = 1.5 V, VFB 20 mV Overdrive. Note 3 Note 3
0.475 - 18 - 0
0.525 80 25 200 -
0.575 - 35 300 1.4
V % mV ns V
-
150
200
250
kHz
COMP = 0 V (No Switching) GATE(H) Switching, COMP Charging GATE(H) Not Switching, COMP Discharging Start - Stop
- 8.0 7.0 0.75
10 8.5 7.5 1.0
15 9.0 8.0 1.25
mA V V V
3. Guaranteed by design. Not tested in production.
PACKAGE PIN DESCRIPTION
PACKAGE PIN # 1 2 3 4 PIN SYMBOL VCC PWRGD PGDELAY COMP Power supply input. Open collector output goes low when VFB is out of regulation. User must externally limit current into this pin to less than 20 mA. External capacitor programs PWRGD low-to-high transition delay. Error amp output. PWM comparator reference input. A capacitor to LGND provides error amp compensation and Soft-Start. Pulling pin < 0.475 V locks gate outputs to a zero percent duty cycle state. High-side switch FET driver pin. Capable of delivering peak currents of 1.5 A. Low-side synchronous FET driver pin. Capable of delivering peak currents of 1.5 A. Error amplifier and PWM comparator input. Power supply return. FUNCTION
5 6 7 8
GATE(H) GATE(L) VFB GND
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Fault Latch S + + - - 8.5 V/7.5 V + + - 0.25 V R Set Dominant Q
VCC
-
UVLO COMP
GND VCC Error Amp - + + + - 0.980 V S Reset Dominant COMP 0.525 V -+ OSC GATE(L) Non Overlap
VFB
-
PWM COMP
PWM Latch R Q GATE(H)
Art Ramp 80%, 200 kHz + -
+ - 12 mA PGDELAY
0.25 V
- + + - 0.88 V/0.69 V
PGDELAY Latch S Q + -
- +
PWRGD
3.3 V
R Set Dominant
Figure 2. Block Diagram
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TYPICAL PERFORMANCE CHARACTERISTICS
10 216 214 212 210 208 206 204 5 0 20 40 60 80 Temperature (C) 100 120 202 0 20 40 60 80 Temperature (C) 100 120
9
ICC (mA)
8
7
6
Figure 3. Supply Current vs. Temperature
Oscillator Frequency (kHz) 0 20 40 60 80 Temperature (C) 100 120
Figure 4. Oscillator Frequency vs. Temperature
0.984 0.983 Reference Voltage (V) 0.982 0.981 0.980 0.979 0.978 0.977 0.976 Ramp Amplitude (mV)
27 26 25 24 23 22 21 20 0 20 40 60 80 Temperature (C) 100 120
Figure 5. Reference Voltage vs. Temperature
Figure 6. Artificial Ramp Amplitude vs. Temperature (50% Duty Cycle)
540 Start/Stop Threshold Voltages (V)
8.6 8.4 8.2 8.0 7.8 7.6 7.4 7.2 0 20 40 60 80 Temperature (C) 100 120 Turn-Off Threshold Turn-On Threshold
PWM Offset Voltage (mV)
535
530
525
520
0
20
40 60 80 Temperature (C)
100
120
Figure 7. PWM Offset Voltage vs. Temperature
Figure 8. Undervoltage Lockout Thresholds vs. Temperature
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TYPICAL PERFORMANCE CHARACTERISTICS
0.60 31 30 Output Current (mA) 0.55 Bias Current (mA) 29 Sink Current 28 27 Source Current 26 25 0.40 0 20 40 60 80 Temperature (C) 100 120 24 0 20 40 60 80 Temperature (C) 100 120
0.50
0.45
Figure 9. VFB Bias Current vs. Temperature
Figure 10. Error Amp Output Currents vs. Temperature
3.5 3.0 COMP Voltages (V) 2.5 2.0 1.5 1.0 0.5 0 0 20 40 COMP Fault Threshold Voltage 60 80 Temperature (C) 100 120 COMP Minimum Voltage COMP Maximum Voltage Discharge Current (mA)
1.20 1.15 1.10 1.05 1.00 0.95 0.90
0
20
40 60 80 Temperature (C)
100
120
Figure 11. COMP Voltages vs. Temperature
Figure 12. COMP Fault Mode Discharge Current vs. Temperature
38 36 GATE Rise/Fall Times (ns) 34 32 30 28 GATEL Rise Time 26 24 22 20 0 20 40 60 80 Temperature (C) 100 120 GATEL Fall Time GATEH Fall Time Gate Non-Overlap Time (ns) GATEH Rise Time
55
50 GATEH to GATEL Delay Time 45 GATEL to GATEH Delay Time
40
35
30
0
20
40 60 80 Temperature (C)
100
120
Figure 13. GATE Output Rise and Fall Times vs. Temperature
Figure 14. GATE Non-Overlap Times vs. Temperature
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TYPICAL PERFORMANCE CHARACTERISTICS
1000 PWRGD Threshold Voltages (mV) Turn-On Threshold, VFB Rising 70 PWRGD Low Voltage (mV) 120 65 60 55 50 45 40
900
800
700 Turn-Off Threshold, VFB Falling 600 0 20 40 60 80 Temperature (C) 100
0
20
40 60 80 Temperature (C)
100
120
Figure 15. PWRGD Thresholds vs. Temperature
Figure 16. PWRGD Output Low Voltage vs. Temperature
13.4 13.1 12.8 12.5 12.2 11.9 11.6 PGDELAY Discharge Current (mA) 0 PGDELAY Charge Current (mA)
1.45 1.40 1.35 1.30 1.25 1.20 1.15
20
40 60 80 Temperature (C)
100
120
0
20
40 60 80 Temperature (C)
100
120
Figure 17. PGDELAY Charge Current vs. Temperature
Figure 18. PGDELAY Discharge Current vs. Temperature
259 Discharge Threshold Voltage (mV)
4.00 3.90 PGDELAY Max Voltage
257
PGDELAY Voltages (V)
3.80 3.70 3.60 3.50 3.40 3.30
255
253
PGDELAY Upper Threshold Voltage
251
0
20
40 60 80 Temperature (C)
100
120
3.20
0
20
40 60 80 Temperature (C)
100
120
Figure 19. PGDELAY Discharge Threshold Voltage vs. Temperature
Figure 20. PGDELAY Voltages vs. Temperature
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APPLICATION INFORMATION
THEORY OF OPERATION
The NCP1571 is a simple, synchronous, fixed-frequency, low-voltage buck controller using the V2 control method. It provides a programmable-delay Power Good function to indicate when the output voltage is out of regulation.
V2 Control Method
The V2 control method uses a ramp signal generated by the ESR of the output capacitors. This ramp is proportional to the AC current through the main inductor and is offset by the DC output voltage. This control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. The V2 method differs from traditional techniques such as voltage mode control, which generates an artificial ramp, and current mode control, which generates a ramp using the inductor current.
-
GATE(H) GATE(L)
PWM
+
RAMP
Output Voltage Error Amplifier
-
Slope Compensation COMP Error Signal
VFB Reference Voltage
+
Figure 21. V2 Control with Slope Compensation
time to the output load step is not related to the crossover frequency of the error signal loop. The error signal loop can have a low crossover frequency, since the transient response is handled by the ramp signal loop. The main purpose of this `slow' feedback loop is to provide DC accuracy. Noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. Line and load regulation are drastically improved because there are two independent control loops. A voltage mode controller relies on the change in the error signal to compensate for a deviation in either line or load voltage. This change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. A current mode controller maintains a fixed error signal during line transients, since the slope of the ramp signal changes in this case. However, regulation of load transients still requires a change in the error signal. The V2 method of control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load. The stringent load transient requirements of modern microprocessors require the output capacitors to have very low ESR. The resulting shallow slope in the output ripple can lead to pulse width jitter and variation caused by both random and synchronous noise. A ramp waveform generated in the oscillator is added to the ramp signal from the output voltage to provide the proper voltage ramp at the beginning of each switching cycle. This slope compensation increases the noise immunity, particularly at duty cycles above 50%.
Startup
The V2 control method is illustrated in Figure 21. The output voltage generates both the error signal and the ramp signal. Since the ramp signal is simply the output voltage, it is affected by any change in the output, regardless of the origin of that change. The ramp signal also contains the DC portion of the output voltage, allowing the control circuit to drive the main switch from 0% to 100% duty cycle as required. A variation in line voltage changes the current ramp in the inductor, which causes the V2 control scheme to compensate the duty cycle. Since any variation in inductor current modifies the ramp signal, as in current mode control, the V2 control scheme offers the same advantages in line transient response. A variation in load current will affect the output voltage, modifying the ramp signal. A load step immediately changes the state of the comparator output, which controls the main switch. The comparator response time and the transition speed of the main switch determine the load transient response. Unlike traditional control methods, the reaction
The NCP1571 features a programmable Soft-Start function, which is implemented through the error amplifier and the external compensation capacitor. This feature prevents stress to the power components and limits output voltage overshoot during startup. As power is applied to the regulator, the NCP1571 undervoltage lockout circuit (UVL) monitors the IC's supply voltage (VCC). The UVL circuit holds both gate outputs low until VCC exceeds the 8.5 V threshold. A hysteresis function of 1.0 V improves noise immunity. The compensation capacitor connected to the COMP pin is charged by a 30 mA current source. When the capacitor voltage exceeds the 0.525 V offset of the PWM comparator, the PWM control loop will allow switching to occur. The upper gate driver GATE(H) is activated, turning on the upper MOSFET. The current ramps up through the main inductor and linearly powers the output capacitors and load. When the regulator output voltage exceeds the COMP pin voltage minus the 0.525 V PWM comparator offset threshold and the artificial ramp, the PWM comparator terminates the initial pulse.
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8.5 V VIN
output voltage, preventing damage to the load. The regulator remains in this state until the overvoltage condition ceases.
Power Good
VCOMP 0.5 V VFB
GATE(H)
UVLO
STARTUP
tS
NORMAL OPERATION
Figure 22. Idealized Waveforms Normal Operation
The PWRGD pin is asserted when the output voltage is within regulation limits. Sensing for the PWRGD pin is achieved through the VFB pin. When the output voltage is rising, PWRGD goes high at 90% of the designed output voltage. When the output voltage is falling, PWRGD goes low at 70% of the designed output voltage. PWRGD is an open-collector output and should be externally pulled to logic high through a resistor to limit current to no more than 20 mA. Figure 23 shows the hysteretic nature of the PWRGD pin's operation.
PWRGD High
During normal operation, the duty cycle of the gate drivers remains approximately constant as the V2 control loop maintains the regulated output voltage under steady state conditions. Variations in supply line or output load conditions will result in changes in duty cycle to maintain regulation.
Input Supplies
The NCP1571 can be used in applications where a 12 V supply is available along with a lower voltage supply. Often the lower voltage supply is 5 V, but it can be any voltage less than the 12 V supply minus the required gate drive voltage of the top MOSFET. The greater the difference between the two voltages, the better the efficiency due to increasing VGS available to turn on the upper MOSFET. In order to maintain power supply stability, the lower supply voltage should be at least 1.5 times the desired voltage. A lower supply voltage between 2-7 V is recommended.
Gate Charge Effect on Switching Times
Low VOUT 70% 90% Percent of Designed VOUT
Figure 23. PWRGD Assertion Shutdown
When using the onboard gate drivers, the gate charge has an important effect on the switching times of the FETs. A finite amount of time is required to charge the effective capacitor seen at the gate of the FET. Therefore, the rise and fall times rise linearly with increased capacitive loading.
Transient Response
When the input voltage connected to VCC falls through the lower threshold of the UVLO comparator, a fault latch is set. The fault latch provides a signal that forces both GATE(H) and GATE(L) into their logic low state, producing a high-impedance output at the converter switch node. At the same time, the latch also turns on two transistors which pull down on the COMP and PGDELAY pins, quickly discharging their external capacitors, and allowing PWRGD to fall.
CONVERTER DESIGN Selection of the Output Capacitors
The 200 ns reaction time of the control loop provides fast transient response to any variations in input voltage and output current. Pulse-by-pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitors during the time required to slew the inductor current. For better transient response, several high frequency and bulk output capacitors are usually used.
Overvoltage Protection
Overvoltage protection is provided as a result of the normal operation of the V2 control method and requires no additional external components. The control loop responds to an overvoltage condition within 200 ns, turning off the upper MOSFET and disconnecting the regulator from its input voltage. This results in a crowbar action to clamp the
These components must be selected and placed carefully to yield optimal results. Capacitors should be chosen to provide acceptable ripple on the regulator output voltage. Key specifications for output capacitors are their ESR Equivalent Series Resistance (ESR), and Equivalent Series Inductance (ESL). For best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required. In order to determine the number of output capacitors the maximum voltage transient allowed during load transitions has to be specified. The output capacitors must hold the output voltage within these limits since the inductor current
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can not change with the required slew rate. The output capacitors must therefore have a very low ESL and ESR. The voltage change during the load current transient is:
DVOUT + DIOUT ESL ) ESR ) tTR Dt COUT
where: DIOUT / Dt = load current slew rate; DIOUT = load transient; Dt = load transient duration time; ESL = Maximum allowable ESL including capacitors, circuit traces, and vias; ESR = Maximum allowable ESR including capacitors and circuit traces; tTR = output voltage transient response time. The designer has to independently assign values for the change in output voltage due to ESR, ESL, and output capacitor discharging or charging. Empirical data indicates that most of the output voltage change (droop or spike depending on the load current transition) results from the total output capacitor ESR. The maximum allowable ESR can then be determined according to the formula:
ESRMAX + DVESR DIOUT
the inrush current into the input capacitors upon power up. The inductor's limiting effect on the input current slew rate becomes increasingly beneficial during load transients. The worst case is when the load changes from no load to full load (load step), a condition under which the highest voltage change across the input capacitors is also seen by the input inductor. The inductor successfully blocks the ripple current while placing the transient current requirements on the input bypass capacitor bank, which has to initially support the sudden load change. The minimum inductance value for the input inductor is therefore:
DV LIN + (dI dt)MAX
where: LIN = input inductor value; DV = voltage seen by the input inductor during a full load swing; (dI/dt)MAX = maximum allowable input current slew rate. The designer must select the LC filter pole frequency so that at least 40 dB attenuation is obtained at the regulator switching frequency. The LC filter is a double-pole network with a slope of -2.0, a roll-off rate of -40 dB/dec, and a corner frequency:
fC + 1 2p LC
where: DVESR = change in output voltage due to ESR (assigned by the designer) Once the maximum allowable ESR is determined, the number of output capacitors can be found by using the formula:
ESRCAP Number of capacitors + ESRMAX
where: L = input inductor; C = input capacitor(s).
Selection of the Output Inductor
where: ESRCAP = maximum ESR per capacitor (specified in manufacturer's data sheet). ESRMAX = maximum allowable ESR. The actual output voltage deviation due to ESR can then be verified and compared to the value assigned by the designer:
DVESR + DIOUT ESRMAX
Similarly, the maximum allowable ESL is calculated from the following formula:
ESLMAX + DVESL DI Dt
Selection of the Input Inductor
A common requirement is that the buck controller must not disturb the input voltage. One method of achieving this is by using an input inductor and a bypass capacitor. The input inductor isolates the supply from the noise generated in the switching portion of the buck regulator and also limits
There are many factors to consider when choosing the output inductor. Maximum load current, core and winding losses, ripple current, short circuit current, saturation characteristics, component height and cost are all variables that the designer should consider. However, the most important consideration may be the effect inductor value has on transient response. The amount of overshoot or undershoot exhibited during a current transient is defined as the product of the current step and the output filter capacitor ESR. Choosing the inductor value appropriately can minimize the amount of energy that must be transferred from the inductor to the capacitor or vice-versa. In the subsequent paragraphs, we will determine the minimum value of inductance required for our system and consider the trade-off of ripple current vs. transient response. In order to choose the minimum value of inductance, input voltage, output voltage and output current must be known. Most computer applications use reasonably well regulated bulk power supplies so that, while the equations below specify VIN(MAX) or VIN(MIN), it is possible to use the nominal value of VIN in these calculations with little error.
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Current in the inductor while operating in the continuous current mode is defined as the load current plus ripple current.
IL + ILOAD ) IRIPPLE
Finally, we should consider power dissipation in the output inductors. Power dissipation is proportional to the square of inductor current:
PD + (I 2)(ESRL) L
The ripple current waveform is triangular, and the current is a function of voltage across the inductor, switch FET on-time and the inductor value. FET on-time can be defined as the product of duty cycle and switch frequency, and duty cycle can be defined as a ratio of VOUT to VIN. Thus,
(VIN * VOUT)VOUT IRIPPLE + (fOSC)(L)(VIN)
The temperature rise of the inductor relative to the air surrounding it is defined as the product of power dissipation and thermal resistance to ambient:
DT(inductor) + (Ra)(PD)
Ra for an inductor designed to conduct 20 A to 30 A is approximately 45C/W. The inductor temperature is given as:
T(inductor) + DT(inductor) ) Tambient VCC Bypass Filtering
Peak inductor current is defined as the load current plus half of the peak current. Peak current must be less than the maximum rated FET switch current, and must also be less than the inductor saturation current. Thus, the maximum output current can be defined as:
IOUT(MAX) + ISWITCH(MAX) * VIN(MAX) * VOUT VOUT 2 fOSC L VIN(MAX)
A small RC filter should be added between module VCC and the VCC input to the IC. A 10 W resistor and a 0.47 mF capacitor should be sufficient to ensure the controller IC does not operate erratically due to injected noise, and will also supply reserve charge for the onboard gate drivers.
Input Filter Capacitors
Since the maximum output current must be less than the maximum switch current, the minimum inductance required can be determined.
(VIN(MIN) * VOUT)VOUT L(MIN) + (fOSC)(ISWITCH(MAX))(VIN(MIN))
The input filter capacitors provide a charge reservoir that minimizes supply voltage variations due to changes in current flowing through the switch FETs. These capacitors must be chosen primarily for ripple current rating.
LIN VIN IIN(AVE) CIN
CONTROL INPUT
This equation identifies the value of inductor that will provide the full rated switch current as inductor ripple current, and will usually result in inefficient system operation. The system will sink current away from the load during some portion of the duty cycle unless load current is greater than half of the rated switch current. Some value larger than the minimum inductance must be used to ensure the converter does not sink current. Choosing larger values of inductor will reduce the ripple current, and inductor value can be designed to accommodate a particular value of ripple current by replacing ISWITCH(MAX) with a desired value of IRIPPLE:
(VIN(MIN) * VOUT)VOUT L(RIPPLE) + (fOSC)(IRIPPLE)(VIN(MIN))
LOUT VOUT COUT
IRMS(CIN)
Figure 24.
Consider the schematic shown in Figure 24. The average current flowing in the input inductor LIN for any given output current is:
IIN(AVE) + IOUT VOUT VIN
However, reducing the ripple current will cause transient response times to increase. The response times for both increasing and decreasing current steps are shown below.
TRESPONSE(INCREASING) + (L)(DIOUT) (VIN * VOUT) (L)(DIOUT) (VOUT)
TRESPONSE(DECREASING) +
Inductor value selection also depends on how much output ripple voltage the system can tolerate. Output ripple voltage is defined as the product of the output ripple current and the output filter capacitor ESR. Thus, output ripple voltage can be calculated as:
VRIPPLE + ESRC IRIPPLE + ESRC VIN * VOUT VOUT fOSC L VIN
Input capacitor current is positive into the capacitor when the switch FETs are off, and negative out of the capacitor when the switch FETs are on. When the switches are off, IIN(AVE) flows into the capacitor. When the switches are on, capacitor current is equal to the per-phase output current minus IIN(AVE). If we ignore the small current variation due to the output ripple current, we can approximate the input capacitor current waveform as a square wave. We can then calculate the RMS input capacitor ripple current:
IRMS(CIN) + V ) OUT I2 IN(AVE) VIN IOUT per phase * IIN(AVE) 2 * I 2 IN(AVE)
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NCP1571
The input capacitance must be designed to conduct the worst case input ripple current. This will require several capacitors in parallel. In addition to the worst case current, attention must be paid to the capacitor manufacturer's derating for operation over temperature. As an example, let us define the input capacitance for a 5 V to 3.3 V conversion at 10 A at an ambient temperature of 60C. Efficiency of 80% is assumed. Average input current in the input filter inductor is:
IIN(AVE) + (10 A)(3.3 V 5 V) + 6.6 A
Input capacitor RMS ripple current is then
IIN(RMS) + 6.62 ) 3.3 V 5V [(10 A * 6.6 A)2 * 6.6 A2]
+ 4.74 A
ohmic power loss. However, placing FETs in parallel increases the gate capacitance so that switching losses increase. As long as adding another parallel FET reduces the ohmic power loss more than the switching losses increase, there is some advantage to doing so. However, at some point the law of diminishing returns will take hold, and a marginal increase in efficiency may not be worth the board area required to add the extra FET. Additionally, as more FETs are used, the limited drive capability of the FET driver will have to charge a larger gate capacitance, resulting in increased gate voltage rise and fall times. This will affect the amount of time the FET operates in its ohmic region and will increase power dissipation. The following equations can be used to calculate power dissipation in the switch FETs. For ohmic power losses due to RDS(ON):
PON(TOP) +
PON(BOTTOM) +
If we consider a Rubycon MBZ series capacitor, the ripple current rating for a 6.3 V, 1800 nF capacitor is 2000 mA at 100 kHz and 105C. We determine the number of input capacitors by dividing the ripple current by the percapacitor current rating:
Number of capacitors + 4.74 A 2.0 A + 2.3
(RDS(ON)(TOP))(IRMS(TOP))2 (number of topside FETs)
RDS(ON)(BOTTOM) IRMS(BOTTOM) 2 number of bottom-side FETs
A total of at least 3 capacitors in parallel must be used to meet the input capacitor ripple current requirements.
Output Switch FETs
where: n = number of phases. Note that RDS(ON) increases with temperature. It is good practice to use the value of RDS(ON) at the FET's maximum junction temperature in the calculations shown above.
IRMS(TOP) + I 2 * (IPK)(IRIPPLE) ) D I 2 PK 3 RIPPLE (1 * D) 2 I RIPPLE 3
Output switch FETs must be chosen carefully, since their properties vary widely from manufacturer to manufacturer. The NCP1571 system is designed assuming that N-Channel FETs will be used. The FET characteristics of most concern are the gate charge/gate-source threshold voltage, gate capacitance, on-resistance, current rating and the thermal capability of the package. The onboard FET driver has a limited drive capability. If the switch FET has a high gate charge, the amount of time the FET stays in its ohmic region during the turn-on and turn-off transitions is larger than that of a low gate charge FET, with the result that the high gate charge FET will consume more power. Similarly, a low on-resistance FET will dissipate less power than will a higher on-resistance FET at a given current. Thus, low gate charge and low RDS(ON) will result in higher efficiency and will reduce generated heat. It can be advantageous to use multiple switch FETs to reduce power consumption. By placing a number of FETs in parallel, the effective RDS(ON) is reduced, thus reducing the
IRMS(BOTTOM) + I 2 * (IPKIRIPPLE) ) PK IRIPPLE +
(VIN * VOUT)(VOUT) (fOSC)(L)(VIN)
I I I IPEAK + ILOAD ) RIPPLE + OUT ) RIPPLE 2 3 2
where: D = Duty cycle. For switching power losses:
PD + nCV2(fOSC)
where: n = number of switch FETs (either top or bottom), C = FET gate capacitance, V = maximum gate drive voltage (usually VCC), fOSC = switching frequency.
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NCP1571
Layout Considerations
1. The fast response time of V2 technology increases the IC's sensitivity to noise on the VFB line. Fortunately, a simple RC filter, formed by the feedback network and a small capacitor (100 pF works well, shown below as C6) placed between VFB and GND, filters out most noise and provides a system practically immune to jitter. This capacitor should be located as close as possible to the IC. 2. The COMP capacitor (shown below as C13) should be connected via its own path to the IC ground. The COMP capacitor is sensitive to the intermittent ground drops caused by switching currents. A separate ground path will reduce the potential for jitter. 3. The VCC bypass capacitor (0.1 mF or greater, shown below as C4) should be located as close as possible to the IC. This capacitor's connection to GND must be as short as possible. The 10 W resistor (shown below as R3) should be placed close to the VCC pin. 4. The IC should not be placed in the path of switching currents. If a ground plane is used, care should be taken by the designer to ensure that the IC is not located over a ground or other current return path.
R4 VOUT R6 C6
C4 R3 U1 R1 GND 12 V PWRGD C13
C12
5V
Figure 25.
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NCP1571
PACKAGE DIMENSIONS
SOIC-8 D SUFFIX CASE 751-07 ISSUE AC
-X- A
8 5
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060 7.0 0.275 4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP1571
V2 is a trademark of Switch Power, Inc.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NCP1571/D

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